The invention relates to an integrated semiconductor memory having memory cells with a ferroelectric memory property. The integrated semiconductor memory has a memory cell field with row lines for selecting memory cells and column lines for reading or writing data signals of the memory cells. The memory cells are in each case connected between one of the column lines and a charge line. The column line is connected to a read amplifier and the charge line is connected to a driver circuit which provides the charge line with a given potential. The column line and the charge line each have an active mode and an inactive mode.
Integrated semiconductor memories having so-called FeRAM memory cells (Ferroelectric Random Access Memory) which have a ferroelectric memory property are often constructed in a similar manner as, for example, DRAMs (Dynamic Random Access Memory). Memory cells in DRAMs are usually combined in a matrix-type memory cell array to form units of column lines and row lines. The column lines are generally connected to a read amplifier at which a data signal to be read out and amplified can be picked up.
In memory cells having a ferroelectric memory property, it is known that data signals are stored in the memory cell in the form of distinguishable polarization states of the material. In the operation of the semiconductor memory, the memory cells generally have a capacitive behavior. Semiconductor memories having such memory cells are known, for example, as so-called FeRAMs. The memory cells are usually connected between one of the column lines and a charge line also called a xe2x80x9cplatexe2x80x9d. This charge line is in most cases connected to a driver circuit through the use of which the charge line is at a given potential.
When operating the semiconductor memory, the column lines and the charge lines of the memory in each case have an active mode and an inactive mode. In the active mode, in which, for example, the content of a memory cell is read out, the corresponding column line is connected to a read amplifier and the charge line is at a given potential. In the inactive mode, the corresponding column lines and the charge lines are generally connected to a connection for a common supply potential.
This is necessary in order to prevent an unintended change of the content of a memory cell, for example due to interfering voltages. Such interfering voltages are produced, for example, by a signal being coupled from an active row line into an inactive charge line. With an active row line, the selection transistor between the memory cell and the relevant column line is in the conducting state. It is essential, especially in this operating state, for an inactive column line and an inactive charge line to have the same potential so that the two poles of the connected memory cell are at the same potential.
The column lines and charge lines which are in an inactive mode are frequently connected to a common voltage network. Such a voltage network generally has comparatively large line capacitances and line resistances caused by relatively large dimensions and line lengths. If, for example, interfering voltages are produced on an inactive column line along an active row line, for example by a signal being coupled in, it is possible that unwanted potential differences occur between this column line and the charge line of a connected memory cell. This is the case, in particular, if the connections of the column line and of the charge line to the voltage network for the common supply potential are spatially separate, that is to say, for example, are connected in different circuit parts of the semiconductor memory. Due to comparatively large line capacitances and line resistances of the voltage network, a necessary equalization of the potential between these lines is delayed in time. Thus, a short-term or transient potential difference can arise at the poles of the memory cells which are provided along an active row line and can change the content of the memory cells in an unintended manner.
It is accordingly an object of the invention to provide an integrated memory circuit which overcomes the above-mentioned disadvantages of the heretofore-known integrated memory circuits of this general type and in which the probability of any unintended change in the memory content of a memory cell due to interfering voltages can be kept comparatively small.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory, including:
a memory cell having a ferroelectric memory property;
a memory cell array including a row line for selecting the memory cell and a column line for reading data signals from the memory cell and writing data signals to the memory cell;
a charge line;
the memory cell being connected between the column line and the charge line;
a read amplifier connected to the column line, the read amplifier supplying an output signal;
a driver circuit connected to the charge line for providing a given potential to the charge line;
a connection for providing a common supply potential; and
the column line and the charge line each having an active operation mode and an inactive operation mode, and, when in the inactive operation mode, the column line and the charge line being jointly connected, in the read amplifier or in the driver circuit, to the connection for providing the common supply potential.
In other words, the object of the invention is achieved by an integrated semiconductor memory having memory cells with a ferroelectric memory property, having a memory cell array which has row lines for selecting memory cells and column lines for reading or writing data signals of the memory cells, in which the memory cells are in each case connected between one of the column lines and a charge line; in which the column line is connected to a read amplifier at which an output signal can be picked up; in which the charge line is connected to a driver circuit through the use of which the charge line can be placed at a predetermined potential; in which the column line and the charge line in each case have an active mode or an inactive mode; in which, in the inactive mode, the column line and the charge line are connected to a connection for a common supply potential; and in which the column line and the charge line are jointly connected to the connection for the supply potential in the read amplifier or in the driver circuit.
Due to the fact that the column line and the charge line are jointly connected to the connection for the common supply potential in the read amplifier or in the driver circuit, the corresponding column line and charge line are connected to the common supply potential in relative proximity to one another. This prevents comparatively large line capacitances and line resistances which are caused by comparatively large dimensions and line lengths of the voltage network. As a result, a relatively quick equalization of potential between the lines is possible in the case where interfering voltages are coupled into the relevant column line and/or charge line. Potential differences at the poles of a memory cell which is connected to an inactive column line and an active row line are kept comparatively small. This prevents any unintended change in the memory content of a memory cell due to interfering voltages.
The invention can be applied, in particular, to a semiconductor memory which is operated with a so-called Pulsed-Plate concept (PPL concept). During a read cycle for reading out a data signal from a memory cell, for example, the relevant column line has an active mode. The column line is connected to the read amplifier at which the data signal can be picked up. The relevant charge line is at a predetermined potential due to the driver circuit. This potential corresponds, for example, to the positive supply potential of the semiconductor memory. In the inactive mode, the relevant column line is separate from the read amplifier and, together with the charge line, connected to the connection for the common supply potential. This supply potential is, for example, a reference potential of the integrated semiconductor memory. Thus, according to a preferred feature of the invention, the connection provides, as the common supply potential, a reference potential for an integrated semiconductor memory.
According to a further feature of the invention, a first switching device is provided, the column line and the charge line being connected to one another via the first switching device; a second switching device is provided, the column line or the charge line being connected to the connection for the common supply potential via the second switching device, the connection for providing the common supply potential being a first connection; and a second connection is provided for supplying a common control signal, the first switching device having a first control connection, the second switching device having a second control connection, the first control connection and the second control connection being connected to the second connection for providing the common control signal.
In other words, the column line and the charge line are connected to one another via a first switching device, the column line or the charge line is connected to the connection for the supply potential via a second switching device. In this configuration, a control connection of the first switching device and a control connection of the second switching device are connected to the connection for a common control signal. This embodiment provides the possibility of a quick equalization of potential in the case of interfering voltages being coupled in, since the relevant column line and the charge line are short-circuited via the first switching device. Both lines are jointly connected to the connection for the supply potential via a common drive of the first switching device and the second switching device.
According to yet another feature of the invention, a third connection for a column select signal is provided; a fourth connection for a row select signal is provided; and a processing unit having an input side connected to the third connection and to the fourth connection is provided, and the processing unit has an output side connected to the first control connection and to the second control connection.
In other words, according to this embodiment of the invention, the integrated semiconductor memory has a processing unit, which is connected at its input to a connection for a column select signal and to a connection for a row select signal. The processing unit is connected at its output to the control connection of the first switching device and to the control connection of the second switching device. The column select signal is generated, for example, by a column decoder for selecting one of the column lines. The row select signal is generated, for example, by a row decoder. Floating states on the column line in other areas of the memory cell array are prevented by logically combining information from the column decoding and row decoding.
According to another feature of the invention, the processing unit includes a logic NAND gate.
The memory cell array is usually subdivided into a number of blocks which in each case include a number of row lines. During a memory access, only the memory cells within a selected block of the memory cell array are generally activated along she selected column line. Driving the processing unit with the row select signal makes it possible to connect the selected column line to the connection for the supply potential in the remaining inactive areas of the memory cell array. A floating state of a selected column line is thus prevented in these memory areas.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory having memory cells with a ferroelectric memory property, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.